High speed serial single- and multi-lane data links and associated devices often introduce distortion in digital signals, which may result in bit errors and bit slip errors in a digital receiver. Examples of such data links that can cause bit errors are links within components, such as for example a 28 Gbit/s quad retimer, between components on a PCB, such as for example an electrical CAUI-4 interface used for 100 Gbit/s transponders, board-to-board links within a system, such as for example electrical backplane links, or system-to-system links, such as for example an optical 100 Gbit/s Ethernet 100 GBASE-LR4 link. Diagnosing and analyzing root causes of such bit errors and bit slips occurring on high speed data links is often difficult and time consuming. The problem is often exacerbated when the errors occur infrequently, for example once a day.
A conventional method of diagnosing such problems is to tap the signal and to analyze it with a high speed Digital Sampling Oscilloscope (DSO) or other suitable analyzer tools. However, tapping of high speed signals is often not possible, for example when the error occurs within a component or a closed subsystem, or because tapping severely distorts the signal. On multi-lane links a necessity to tap multiple signals in parallel might exacerbate the difficulties. In addition, the signals are often severely distorted and judgment of the signal quality may not be possible without complex preprocessing, for example by means of an equalizer. Even if such preprocessing is available, it is often not possible or at least difficult to deduce which portion of the signal causes bit errors at the receiver. Furthermore, DSOs or similar test equipment with a high enough measurement bandwidth can be extremely expensive or simply non-existent, such as in the case of very high speed links. As a result, the root causes of bit errors often remain unclear.
Therefore, technicians are often forced to work in the dark when trying to determine and remove root cause of bit errors in a data link. Typically a trial and error approach is used, which includes tuning a number of parameters, such as output level, de-emphasis, equalizer, slicer level, sampler phase, etc., while making bit error rate (BER) measurements for every parameter combination tried. This process is often very time consuming, in part because each BER measurement can take a long time when errors are infrequent, and also because tuning of the various parameters influence the measurement result in a hard to predict and mutually dependent manner.
An object of the present invention is to provide a method and/or device for bit error analysis that correlates bit errors with specific bit patterns and related signal characteristics thereby enabling a quick estimation of likely causes of the bit errors.